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? semiconductor components industries, llc, 2015 august, 2015 ? rev. 0 1 publication order number: r281/d belasigna r281 always-listening, voice trigger solution introduction belasigna ? r281 is an ultra?low?power voice trigger solution for a wide range of consumer electronic devices. in a typical application belasigna r281 is ?always listening? and will detect a single, user?trained trigger phrase, asserting a wake?up signal when this trigger phrase is detected. ?always?listening? key phrase detection with an average power consumption of less than 300 w (not including the power consumption of the microphone) preserves standby battery life. belasigna r281 is an ultra?miniature solution that is available in both a 5 mm x 5 mm qfn32 package (488am) and a 2.42 mm x 2.74 mm wlcsp package (available soon). it can be designed onto a single layer pcb with 4 mil routing and with a minimal amount of external components. an external, i 2 c host controller is required to configure the device for operation. key features proven ultra?low?power digital signal processing (dsp) technology ? audio dsp technology originally developed for hearing aids offers the required computational power at extremely low current consumption ? < 300 w average current consumption (not including microphone) mixed?signal system?on?chip (soc) ? audio?grade, analog input with onboard pre?amplifier ? built?in, regulated voltages including onboard microphone bias (1 v or 2 v) for power efficient operation ? supports analog or digital microphone input interfaces and peripherals ? i 2 c?based device configuration and control ? gpio wake signal ? internal oscillator applications ? mobile phones ? tablets ? portable electronic devices ? wearables ? toys see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information marking diagram 0w689?001 = specific device code a = assembly location wl = wafer lot yy = year ww = work week = pb?free package 32 1 qfn32 case 488am 0w689? 001 awlyyww 1 www. onsemi.com
belasigna r281 www. onsemi.com 2 figures and data table 1. absolute maximum ratings parameter symbol min max units input voltage on any digital pin ?0.3 3.8 v input voltage on any analog pin ?0.3 3.8 v input voltage on any supply pin ?0.3 3.8 v current on any digital pin 5 ma current on any analog pin 10 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. table 2. recommended operating conditions parameter symbol min typ max units power supply applied to vbat vbat 1.75 1.8 qfn 3.63 v wlcsp 1.98 power supply applied to vddo vddo 1.75 1.8 3.63 v internal oscillator clock frequency 1 2.56 20 mhz ambient operating temperature range ta ?40 85 c table 3. esd and latch?up characteristics parameter conditions max units esd ? human body model jedec js 001 2010, all pins 2000 v esd ? charged device model jesd22 c101 e, all pins 750 v esd ? machine model jese22 a115 c, all pins 250 v latch up jedec std 78, all pins 100 ma electrical performance specifications typical values unless otherwise noted, typ values specify the typical values based on design and characterization data under normal operating conditions. normal operating conditions include a supply voltage (vbat) of 1.8 v and an operating temperature of 25 c. for specific blocks, the details of the normal operation conditions are described in their respective sections. minimum and maximum values unless otherwise noted, min and max values specify the designed range or measurement range and are guaranteed by design and/or characterization. min and max values specified may be based on factory production test limits, design, or characterization data. normal operating conditions unless otherwise noted, normal operating conditions indicate an ambient temperature ta = 25 c and a supply voltage vbat = 1.8 v. vddd and vdda are calibrated to their preset factory calibration settings and correspond to their respective typ values. vddo is powered externally at 1.8 v. no external loads are applied to digital i/o or analog pins. table 4. system dc electrical characteristics typical operating conditions (ta = 25 c, vbat=vddo=1.8 v, vddd=1.4 v) unless otherwise noted parameter symbol conditions min typ max units average run mode current idd vbat=vdda=1.8 v, charge pump disabled assumes a ratio of speech present versus quiet environment of 20/80 170 a
belasigna r281 www. onsemi.com 3 table 5. digital i/o pins (i2c, wake_up, dmic) dc electrical characteristics typical operating conditions (ta = 25 c, vddo = 1.8 v, pull up/pull down enabled) unless otherwise noted parameter symbol conditions min typ max units vddo supply voltage range vddo 1.25 1.8 3.63 v output low level v ol i ol = 4 ma 0 0.2 x vddo v output high level v oh i ol = ?4 ma 0.8 x vddo vddo v input low level v il 0 0.2 x vddo v input high level v ih 0.8 x vddo vddo v pull?up resistance r pu non?i 2 c vddo = 1.8 v 80 122 160 k vddo = 3.3 v 30 48 60 i 2 c (strong/weak) vddo = 1.8 v 0.8 / 8 1 / 10 1.2 / 12 vddo = 3.3 v 0.8 / 8 1 / 10 1.2 / 12 pull?down resistance r pd vddo = 1.8 v 120 168 210 k vddo = 3.3 v 30 60 80 pin capacitance c pd 5 pf maximum output current i ol , i oh 4 ma input leakage current i l 1 a table 6. vdda regulator dc & ac electrical characteristics typical operating conditions (ta = 25 c), unless otherwise noted parameter symbol conditions min typ max units output voltage vdda cl = 1 f 1.8 1.98 2.0 v load current 4 ma load regulation 5 mv/ma line regulation 20 mv/v psrr @ 1 khz unloaded 20 db table 7. vreg regulator dc & ac electrical characteristics typical operating conditions (ta = 25 c), unless otherwise noted parameter symbol conditions min typ max units output voltage vreg cl = 1 f 0.95 1.0 1.05 v load current 2 ma load regulation 20 mv/ma line regulation 5 mv/v psrr @ 1 khz unloaded 40 db table 8. vddd regulator dc & ac electrical characteristics typical operating conditions (ta = 25 c), unless otherwise noted parameter symbol conditions min typ max units output voltage vddd cl = 1 f 1.2 1.4 1.7 v load current 15 ma load regulation 10 mv/ma line regulation 20 mv/v psrr @ 1 khz unloaded 20 db
belasigna r281 www. onsemi.com 4 system diagrams figure 1. belasigna r281 system diagram (analog microphone, vbat = 1.8 v) figure 2. belasigna r281 system diagram (analog microphone, vbat = 3.3 v)
belasigna r281 www. onsemi.com 5 figure 3. belasigna r281 system diagram (digital microphone, vbat = 1.8 v) figure 4. belasigna r281 system diagram (digital microphone, vbat = 3.3 v)
belasigna r281 www. onsemi.com 6 description of operation efficient implementation of the trigger phrase recognition algorithm is accomplished through the use of three processing units running concurrently. in addition to the main dsp core performing system configuration and signal processing, an input/output processor continuously collects frames of input speech signals which are analyzed by a highly optimized frequency domain co?processor. there are two main modes of operation: recognition mode and training mode. recognition mode when in recognition mode, the entire system remains in an extremely low?power, ?always?on? state continuously listening for speech. when speech is detected, the algorithm proceeds to extract features from the collected audio data, comparing these features to a known set of data computed during the training process. if the features appear to be similar enough to the trained feature data, a match is indicated on the wake_up pin. once the feature extraction and comparison is complete, the system returns to its original low?power state, once again waiting until speech is detected. training mode before belasigna r281 can be placed into recognition mode, it must be trained. training involves recording and analyzing three utterances of a trigger phrase . a trigger phrase can be any collection of words or sounds, in any language, up to a maximum length of approximately 1.5 seconds. when speaking a given phrase, a human will naturally say the same phrase subtly different each time. having multiple instances of the same phrase, each slightly different, helps to make the matching algorithm more robust. training must be performed in a quiet environment, or the trigger phrase match results in recognition mode will be unpredictable. belasigna r281 is placed into training mode by issuing an appropriate setmode command via i 2 c. the algorithm stores relevant feature data from the three separate utterances of the trigger phrase, also known as training templates . once training is complete, the training templates can be read from memory and stored of fline. this template data can then be loaded into memory in the event of a power cycle and the device can be placed directly into recognition mode, thus avoiding the need to re?train the device. this same procedure can be used to recognize multiple trigger phrases, provided they have each been individually trained and stored offline. only one trigger phrase can be active at any one time. refer to and9267/d for more information on the different modes, as well as a description of the i 2 c host control protocol. initial power?on state when belasigna r281 is powered on, the device will perform a brief initialization procedure and then wait for a connection to be made from an external host via i 2 c. at this point, the host controller must connect to belasigna r281 and load its memory with the algorithm binary image, as well as the training template data. once this has been completed, th e device can be put into recognition mode. if no training template data is available (e.g. the training procedure has never been performed), then belasigna r281 must be placed into training mode and the training procedure performed before entering recognition mode. whenever power is removed from the device, the contents of memory are lost and must be re?loaded. for more information refer to and9267/d.
belasigna r281 www. onsemi.com 7 system performance recognition rate performance has been measured in various noise conditions and is shown in figure 5. tests were performed in a sound isolation booth with a series of pre?recorded trigger and non?trigger phrases playing continuously, mixed with varying levels of noise. recognition rate is 100% in a quiet environment (no noise playing). the system was trained in a quiet environment. in all cases, the false trigger rate (the number of times the system triggered on a non?trigger phrase) was 0%. figure 5. recognition rate versus snr current consumption average current consumption was also measured with the device operating in a pure noise environment with no speech present. the results are presented in table 9. table 9. average current consumption condition average current consumption (ua), vbat = 1.8 v quiet environment 160 babble noise 170 *not including microphone current consumption single user operation because belasigna r281 performs recognition based on a training procedure performed by a specific individual, recognition of the trigger phrase is effectively ?single?user?. only the person who trained the system (or an individual with an extremely similar voice print) will be able to reliably trigger the device. digital interfaces wake up pin the wake up pin is a digital output (referenced to vddo) which is used to indicate that the trigger phrase was detected. it is intended to be connected to a digital input of an external host, and its behavior (active high versus active low and duration) is configurable via i 2 c. for more information refer to and9267/d. boot select pin this pin is reserved for future purpose and must be connected to vdda. inter ic communication (i 2 c) interface the i 2 c interface is an industry?standard interface that can be used for high?speed transmission of data between belasigna r281 and an external device. the interface operates at speeds up to 100 kbit/sec, and always operates in slave mode at an address of 0x62.
belasigna r281 www. onsemi.com 8 digital microphone (dmic) interface the digital microphone interface provides a means of interfacing a digital microphone to the system instead of an analog microphone. when the device is configured to use a digital microphone input instead of an analog microphone input (the default), an appropriate clock is output on the dmic_clk pin and device accepts pdm signals from a digital microphone on the dmic_dat input pin. a separate algorithm binary image is available supporting a digital microphone input. figure 6 shows the timing of the dmic interface. for more information refer to and9267/d. figure 6. dmic timing diagram dmic_clk dmic_dat right data 0 left data 0 right data 1 left data 1 right data 2 t hold t hold t setup t setup
belasigna r281 www. onsemi.com 9 mechanical information and circuit design guidelines belasigna r281 is available in two packages: 1. a 5 x 5 mm qfn32 package 2. a 2.42 x 2.74 mm ultra?miniature wafer?level chip scale package (wlcsp) table 10. pin description qfn32 pin # wlcsp ball index name description pad type pull 9 a1 vbat main power supply p 6 f2 vssa analog ground p 8 n/a vddana analog supply voltage (output), capacitor to vssa, or connected to vbat (max. 1.98 v) a 5 e1 vreg analog supply voltage (output), capacitor to vssa a 11 b2 cap0 charge pump capacitor to cap1 a 10 d2 cap1 charge pump capacitor to cap0 a 7 c1 vdda analog supply voltage (output), capacitor to vssa, or connected to vbat (max. 1.98 v) p 4 h2 vmic analog microphone supply output a 1 i1 n/a no connection nc 32 k1 mic0 analog microphone input ai 31 m1 n/a no connection nc 30 l2 n/a no connection nc 29 m3 n/a no connection nc 3 k3 n/a no connection nc 2 j2 n/a no connection nc 14 a3 n/a no connection nc 13 c3 n/a no connection nc 12 e3 boot_sel boot selection (always connect to vdda) ai 17 a5 vddo digital i/o supply, capacitor to vssd, typically connected to vbat p 18 e5 vddd digital supply, capacitor to vssd p 19 c5 vssd digital core and i/o ground, connect to vssa on pcb p 28 i3 n/a no connection nc 21 k5 wake_up wake up signal (output) dio 22 i5 n/a no connection nc 23 h4 n/a no connection nc 24 f4 n/a no connection nc 26 j4 n/a no connection nc 27 l4 dmic_dat digital microphone data input (optional) dio 15 b4 i2c_scl i 2 c clock dio pu 16 d4 i2c_sda i 2 c data dio pu (note 1) 25 m5 dmic_clk digital microphone clock (optional) dio pu (note 2) 20 g3 n/a no connection nc 1. the value of the i 2 c pull?ups is 10 k 2. pull?up is disabled when the dmic interface is enabled. legend: type: a = analog; d = digital; i = input; o = output; p = power; nc = not connected pull: pu = pull up; pd = pull down all digital pads have a schmitt trigger input
belasigna r281 www. onsemi.com 10 reflow information the reflow profile depends on the equipment that is used for the re?flow and the assembly that is being re?flowed. information from jedec standard 22?a113d and j?std?020d.01 can be used as a guideline. electrostatic discharge (esd) device caution: esd sensitive device. permanent damage may occur on devices subjected to high?energy electrostatic discharges. proper esd precautions in handling, packaging and testing are recommended to avoid performance degradation or loss of functionality. ordering information to order belasigna r281, please contact your account manager and ask for part number BR281Q32A101V1G. chip identification chip identification information can be retrieved using the getchipid i 2 c command. the key identifier components and values are as follows for the different package options: refer to and9267/d for more details regarding supported i 2 c commands. company or product inquiries for more information about on semiconductor sales products or services visit our website at http://onsemi.com . ordering information part number package option chip id BR281Q32A101V1G qfn32 0x5000
belasigna r281 www. onsemi.com 11 package dimensions qfn32 5x5, 0.5p case 488am issue a seating note 4 k 0.15 c (a3) a a1 d2 b 1 9 17 32 e2 32x 8 l 32x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.35 0.30 3.35 32x 0.63 32x 5.30 5.30 l1 detail a l alternate terminal constructions l ??? 0.80 a1 ??? a3 0.20 ref b 0.18 d 5.00 bsc d2 2.95 e 5.00 bsc 2.95 e2 e 0.50 bsc 0.30 l k 0.20 1.00 0.05 0.30 3.25 3.25 0.50 ??? max ??? l1 0.15 e/2 note 3 pitch dimension: millimeters recommended a m 0.10 b c m 0.05 c on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. r281/d belasigna is a registered trademark of semiconductor components industries, llc. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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